Memory cell configuration and corresponding production process

US6472696B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ulrich Zimmermann · Waldbrunn, DE
• Thomas Böhm · Zorneding, DE
• Manfred Hain · Vaterstetten, DE
• Armin Kohlhase · Neubiberg, DE
• Yoichi Otani · Radeberg, DE
• Andreas Rusch · Dresden, DE
• Alexander Truby · Dresden, DE

Key dates

• Filing date: Aug 25, 2000
• Grant date: Oct 29, 2002
• Expiry date: Aug 25, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00

Abstract

The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.