Deep trench DRAM with SOI and STI

US6472702B1 · kind B1 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventor

• Wei Shen · Palo Alto, US

Key dates

• Filing date: Feb 1, 2000
• Grant date: Oct 29, 2002
• Expiry date: Feb 1, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0385

Abstract

A method of forming dynamic random access memory (DRAM) comprising a deep trench capacitor with two electrodes and a node dielectric. The deep trench capacitor is formed by etching a deep trench, making a node dielectric on the surface of the trench, and filling the trench with poly-Si. The method also employs silicon on insulator (SOI) technology to form a single crystal Si layer on an insulator above the trench. The SOI is then contacted with the poly-Si electrode of the trench capacitor, and a transistor is fabricated above the trench capacitor. The method enables fabrication of a transistor above the trench capacitor and thereby frees space on the DRAM chip to allow for a greater density of devices on the DRAM chip.