Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same
US6472741B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2001 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jul 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on he substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced beat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency. In addition, the heat spreader can serve as a grounding plane to the package chips, so that the packaged chips would have better electrical performance during operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.