Semiconductor device having a shortened wiring length to reduce the size of a chip
US6472749B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 2, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Feb 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.