Very low quiescent current regulator and method of using
US6472857B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2001 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Apr 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Voltage regulator (10) provides current sense comparator (18) to detect the normal and standby modes of operation for voltage regulator (10). During a normal mode of operation, current sense comparator (18) de-asserts signal (MODE), causing voltage regulator (10) to regulate the output voltage to a predetermined level. Once the current (Iin) has diminished below a predetermined value, current sense comparator (18) asserts signal (MODE) to indicate a standby mode. During the standby mode, regulator (10) regulates the output voltage (Vout) between first and second reference levels, requiring a quiescent current level much less than the quiescent current level required during normal mode, due to the deactivation of current sense comparator (18) and error amplifier (28) during standby mode. An alternate method of quiescent current reduction uses switched voltage reference (86). Bandgap reference (80) supplies voltage reference (Vref1) during normal mode of operation and depletion MOS reference supplies voltage reference (Vref1) during standby mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.