Double data rate input and output in a programmable logic device
US6472904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-functional programmable I/O buffer in a Field Programmable Gate Array (FPGA) device. The I/O buffer is programmably configurable to meet any of a wide range of I/O standards, be it single ended or differential, 5V, 3.3V, 2.5V or 1.5V logic, without the need for implementing multiple I/O buffers to properly handle each different iteration of I/O requirements. An embedded, internal programmable resistor (e.g., a programmable 100 ohm resistor) is programmably selected for use in differential I/O applications, thus eliminating the conventional requirement for the use of an external resistor connected to each differential receiver I/O pin. The present invention also separates I/O pads into groups in each of a plurality of banks in a programmable device (e.g., PLD, FPGA, etc.), with each group being separately powered by the user. The disclosed multi-functional I/O buffer may be programmably configured by the user to be, e.g., a single ended receiver or transmitter, a reference receiver or transmitter, or a differential receiver or transmitter. The pad logic of the multi-functional I/O buffer may include a double data rate input and output mode, each of which includes two flip-fl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.