Delivering a fine delay stage for a delay locked loop

US6472921B1 · kind B1 · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Rajashekhar Rao · Birkenfeld, DE
• Patrick Heyne · Hersbruck, DE

Key dates

• Filing date: May 31, 2001
• Grant date: Oct 29, 2002
• Expiry date: May 31, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K2005/00208
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A circuit, for use in a delay locked loop, provides a phase-shifted output relative to a first signal. The circuit includes plural current sources, current source switches that are selectable to transmit varying amounts of current from the plural current sources, and input switches that receive current via the current source switches and provide the phase-shifted output. The output switches include a first switch for receiving the first signal and a second switch for receiving a second signal phase-shifted from the first signal. The phase-shifted output relative to the first signal is based on an amount of current that passes through each input switch.