Patent · US Expired

Layout of a sense amplifier with accelerated signal evaluation

US6473324B2 · kind B2 · utility

1Cited by

6References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Helmut Fischer · Calw, DE
Michael Markert · Augsburg, DE
Helmut Schneider · Hersbruck, DE
Sabine Schoniger · Hersbruck, DE

Key dates

Filing date	May 4, 2001
Grant date	Oct 29, 2002
Priority date	—
Expiry date	May 4, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4091
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A layout of a sense amplifier configuration for a semiconductor memory is described. The layout has a plurality of read/write amplifiers, extending as strips in the form of rows one under the other, and having NMOS and PMOS transistors. At least one of the two driver transistors is disposed with its doping regions between the associated NMOS or PMOS transistors of the read/write amplifiers. A gate of the driver transistor is configured as a two-strip gate, in order to accelerate the signal evaluation in the sense amplifiers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.