Redundancy architecture for an interleaved memory
US6473339B2 · kind B2 · utility
26Cited by
6References
26Claims
0Family size
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Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Mar 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of packets each including redundancy columns. The packets are divided into two subsets of packets. Each packet is addressable independently from the other by respective address circuits. Each packet also provides redundancy columns exclusively for a respective semi-array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.