Reading method and circuit for a non-volatile memory
US6473340B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Mar 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.