Bitline/dataline short scheme to improve fall-through timing in a multi-port memory
US6473357B1 · kind B1 · utility
17Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 29, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Sep 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a memory array having a first port and a one or more other ports and a control circuit configured to couple (i) a bitline of the first port to a corresponding bitline of the one or more other ports and (ii) a dataline of the first port to a corresponding dataline of the one or more other ports in response to the first port and the one or more other ports accessing a common address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.