Processor development systems
US6473727B1 · kind B1 · utility
10Cited by
17References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1999 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Mar 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A processor including in-circuit emulation means comprising a plurality of scan chains of serially connected registers coupled to a means for enabling a serial scan procedure to be carried out, a first scan chain including an address register for providing an address on an address bus to memory, and means for incrementing the value in the address register under control of the processor, the scan chains being arranged to control the processor for incrementing the address register, and the scan chains including a data register coupled to the data bus of the memory to read/write data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.