Partition of on-chip memory buffer for cache
US6473835B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2002 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jan 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n−1)-way associative cache, so that one associative column of the cache is left unused, although the cache has the same memory array size as a typical n-way associative cache. The extra column of data in the cache is organized as an independent logical translation look-aside buffer (TLB) that is n-way associative. Thus, there is no separate TLB array for the cache, rather, the TLB is contained within the data cache array. In this way, the cache can be implemented with a single chip, and can be of relatively large size, on the order of 8 MB or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.