Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid
US6473883B1 · kind B1 · utility
6Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2001 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Nov 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for improving integrated circuit by using a patterned bump layout on a layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.