Tyler Thorp
69Patents
11h-index
19Co-inventors
71Inventor score
Filing activity: Sep 14, 2000 → May 29, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7023260B2 | Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor | Electricity | 111 | Expired |
| US7656734B2 | Methods and apparatus for extending the effective thermal operating range of a memory | Physics | 75 | Active |
| US7764534B2 | Two terminal nonvolatile memory using gate controlled diode elements | Electricity | 26 | Active |
| US6686785B2 | Deskewing global clock skew using localized DLLs | Electricity | 25 | Expired |
| US7391638B2 | Memory device for protecting memory cells during programming | Physics | 23 | Active |
| US6476663B1 | Method for reducing supply noise near an on-die thermal sensor | Electricity | 18 | Expired |
| US6549038B1 | Method of high-performance CMOS design | Electricity | 18 | Expired |
| US7558129B2 | Device with load-based voltage generation | Physics | 13 | Active |
| US7696805B2 | Level shifter circuit incorporating transistor snap-back protection | Electricity | 12 | Active |
| US7542338B2 | Method for reading a multi-level passive element memory cell array | Physics | 11 | Active |
| US7236023B2 | Apparatus and methods for adaptive trip point detection | Electricity | 11 | Expired |
| US6662126B2 | Measuring skew using on-chip sampling | Physics | 11 | Expired |
| US7999529B2 | Methods and apparatus for generating voltage references using transistor threshold differences | Emerging Cross-Sectional Technologies | 8 | Active |
| US7870472B2 | Methods and apparatus for employing redundant arrays to configure non-volatile memory | Physics | 8 | Active |
| US7542337B2 | Apparatus for reading a multi-level passive element memory cell array | Physics | 6 | Active |
| US6566758B1 | Current crowding reduction technique for flip chip package technology | Electricity | 6 | Expired |
| US6721936B2 | Shield assignment using preferential shields | Electricity | 6 | Expired |
| US6501328B1 | Method for reducing peak to peak jitter in a dual-loop delay locked loop | Electricity | 6 | Expired |
| US8040721B2 | Creating short program pulses in asymmetric memory arrays | Physics | 6 | Active |
| US6483341B2 | CMOS-microprocessor chip and package anti-resonance apparatus | Electricity | 6 | Expired |
| US6473883B1 | Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid | Physics | 6 | Expired |
| US6604226B2 | Verifying on-chip decoupling capacitance using transistor and capacitor surface area information | Physics | 5 | Expired |
| US7515488B2 | Method for load-based voltage generation | Physics | 5 | Active |
| US6871290B2 | Method for reducing a magnitude of a rate of current change of an integrated circuit | Electricity | 4 | Expired |
| US7773446B2 | Methods and apparatus for extending the effective thermal operating range of a memory | Physics | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.