Transistor with shaped gate electrode and method therefor
US6475841B1 · kind B1 · utility
17Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jun 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor structure includes a retrograde gate structure (112) that is narrower at the end that interfaces with the gate dielectric (120) than it is at the opposite end and method for manufacture of such a structure. The retrograde gate structure (112) is formed by depositing a layer of gate material (104) that has varying composition in the vertical direction. The differentiation in composition causes varying lateral etch rate characteristics along the vertical direction of the gate structure (112) such that increased etching of the gate material (104) occurs near the interface with the gate dielectric layer (102).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.