Inventor · Austin, TX, US

Nigel G. Cave

32Patents
10h-index
44Co-inventors
75Inventor score

Filing activity: Jun 3, 1998 → Apr 18, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US6037668A Integrated circuit having a support structure Electricity 83 Expired
US6313024A Method for forming a semiconductor device Electricity 51 Expired
US10026824B1 Air-gap gate sidewall spacer and method Electricity 31 Active
US6127258A Method for forming a semiconductor device Electricity 30 Expired
US9929157B1 Tall single-fin fin-type field effect transistor structures and methods Electricity 21 Active
US6232235A Method of forming a semiconductor device Electricity 19 Expired
US6475841B1 Transistor with shaped gate electrode and method therefor Electricity 17 Expired
US7109051B2 Method of integrating optical devices and electronic devices on an integrated circuit Electricity 15 Expired
US6924184B2 Semiconductor device and method for forming a semiconductor device using post gate stack planarization Electricity 15 Expired
US10236218B1 Methods, apparatus and system for forming wrap-around contact with dual silicide Electricity 12 Active
US7262105B2 Semiconductor device with silicided source/drains Electricity 8 Expired
US7067342B2 Method of integrating optical devices and electronic devices on an integrated circuit Electricity 8 Expired
US10290549B2 Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same Electricity 6 Active
US7144784B2 Method of forming a semiconductor device and structure thereof Electricity 6 Expired
US6372665B1 Method for forming a semiconductor device Electricity 6 Expired
US10381459B2 Transistors with H-shaped or U-shaped channels and method for forming the same Electricity 6 Active
US9947589B1 Methods of forming a gate contact for a transistor above an active region and the resulting device Electricity 5 Active
US10204994B2 Methods of forming a semiconductor device with a gate contact positioned above the active region Electricity 4 Active
US6566264B1 Method for forming an opening in a semiconductor device substrate Electricity 3 Expired
US10249728B2 Air-gap gate sidewall spacer and method Electricity 3 Active
US10734525B2 Gate-all-around transistor with spacer support and methods of forming same Electricity 2 Active
US7470624B2 Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation Emerging Cross-Sectional Technologies 2 Active
US10211100B2 Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor Electricity 2 Active
US10468300B2 Contacting source and drain of a transistor device Electricity 1 Active
US9978608B2 Fin patterning for a fin-type field-effect transistor Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.