Method of manufacturing a super-junction semiconductor device with an conductivity type layer
US6475864B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jan 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing reduces costs and provides an excellent mass-productivity, super-junction semiconductor device, which facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double difflusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, the oxide film is removed by ion etching, and trenches are dug. The p-type epitaxial layers are buried in the trenches by selective epitaxial growth, and the remaining oxide film is removed. The portions of n-type semiconductor substrate not etched off remain as n-type drift regions, resulting in an alternating conductivity type layer formed of n-type drift r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.