Semiconductor device capable of enhancing a withstand voltage at a peripheral region around an element in comparison with a withstand voltage at the element
US6476458B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 28, 2001 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Nov 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has an element region including MOS structure. A p-well region, a connecting impurity diffused region, and an impurity diffused region for guard ring are formed in an n-type semiconductor layer so as to form a well region, The well region has a step defining a higher portion and a lower portion lower than the higher portion so that the impurity diffused region for guard ring is located at the lower portion. The lower portion is located at a periphery of the element region. In this structure, the impurity diffused region for guard ring is completely depleted while the connecting impurity diffused region is partially depleted so that a portion having carriers remains therein while a depletion layer expands in the connecting impurity diffused region before a breakdown due to a reverse bias occurs in the element region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.