Integrated circuit package with improved ESD protection for no-connect pins
US6476472B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Aug 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) package includes an IC having at least one ESD protection circuit that provides protection against electrostatic discharge. The IC has a plurality of bond pads that are not coupled to the ESD protection circuit. The IC is connected to a substrate. The substrate has a first plurality of conductive traces, which are connected to respective bond pads of the IC, and a second plurality of conductive traces, which are not connected to any of the plurality of bond pads of the IC. Either the substrate or the IC has a common conductive trace that is connected to the ESD protection circuit. Each of the second plurality of conductive traces is connected to the common conductive trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.