Packaged semiconductor with multiple rows of bond pads and method therefor
US6476506B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Sep 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/20752
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die has three rows or more of bond pads with minimum pitch. The die is mounted on a package substrate having three rows or more of bond fingers and/or conductive rings. The bond pads on the outermost part of the die (nearest the perimeter of the die) are connected by a relatively lower height wire achieved by reverse stitching to the innermost ring(s) or row (farthest from the perimeter of the package substrate) of bond fingers. The innermost row of bond pads is connected by a relatively higher height wire achieved by ball bond to wedge bond to the outermost row of the bond fingers. The intermediate row of bond pads is connected by relatively intermediate height wire by ball bond to wedge bond to the intermediate row of bond fingers. The varying height wire allows for tightly packed bond pads. The structure is adaptable for stacked die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.