Ring oscillator design for MOSFET device reliability investigations and its use for in-line monitoring
US6476632B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Aug 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2824
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of determining the effect of the degradation of MOSFET on the frequency of a Ring Oscillator (RO) consisting of an odd prime number of inverter stages, each of the inverters stages having an NMOS and a PMOS field-effect transistor is described. The method includes the steps of: a) selecting one inverter from the inverter stages of the RO, the selected inverter having testable nodes, the testable nodes being connected to inputs and outputs of the NMOS and a PMOS field-effect transistors (FET) forming the selected inverter; b) simultaneously stressing under a set of stress conditions 1) all of the NMOS FETs of each of the inverter stages, 2) all of the PMOS FETs, and 3) all of the NMOS FETs and PMOS FETs in the RO; c) measuring a shift in selected device parameters in the selected inverter; d) measuring a frequency degradation of the entire RO; and e) establishing a relationship between the shift in the device parameters and the frequency degradation and relating the relationship to a known degradation mechanism Furthermore, on-chip pass gates controlled by appropriate off-chip DC voltage signals, allow parallel DC stressing, as well as forcing an off-chip AC voltage wavefor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.