Delay locked loop for use in synchronous dynamic random access memory
US6476652B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Oct 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (DLL) is used to compensate for a skew in a synchronous dynamic random access memory. The delay locked loop includes: a delay model for delaying an external clock signal by the skew to generate a delayed clock signal; a signal generation unit, in response to the external clock signal and the delayed clock signal, for generating control signals; a first delay unit, in response to the control signals, for delaying the delayed control signal to generate a first DLL clock signal, wherein the first delay unit has a large unit delay; and a second delay unit, in response to the control signals, for delaying the first DLL clock signal to generate a second DLL clock signal, wherein the second delay means in a small unit delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.