Circuit configuration for deactivating word lines in a memory matrix
US6477106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2001 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Aug 8, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit configuration for deactivating word lines in a memory matrix. The circuit configuration contains controllable connection devices for connecting the relevant word line to a common supply line system carrying the deactivation potential for the word lines. The circuit configuration contains a control circuit that, in response to a deactivation command, produces a deactivation control signal that turns on the controllable connection devices. A reduction device is provided which can be switched on selectively and which, when switched on, limits the currents flowing through the turned-on connection devices to such an extent that the total current flowing via the supply line system does not exceed a prescribed value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.