Method and apparatus for interfacing between systems operating under different clock regimes with interlocking to prevent overwriting of data
US6477170B1 · kind B1 · utility
22Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 1999 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | May 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for interfacing a central processing unit to a network switch with an external memory that transfers data to the network switch at a different clock speed than transfers of data to the central processing unit provides an interlocking mechanism to prevent overwriting of data and underflows from occurring. The interlocking of the state machines, accomplished by the idling and advancing of a processor state machine and an external memory state machine, prevents either one of the separate state machines from outrunning the other state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.