Prioritized instruction scheduling for multi-streaming processors
US6477562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1998 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Dec 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-streaming processor has multiple streams for processing multiple threads, and an instruction scheduler including a priority record of priority codes for one or more of the streams. The priority codes determine in some embodiments relative access to resources as well as which stream has access at any point in time. In other embodiments priorities are determined dynamically and altered on-the-fly, which may be done by various criteria, such as on-chip processing statistics, by executing one or more priority algorithms, by input from off-chip, according to stream loading, or by combinations of these and other methods. In one embodiment a special code is used for disabling a stream, and streams may be enabled and disabled dynamically by various methods, such as by on-chip events, processing statistics, inpu from off-chip, and by processor interrupts. Some specific applications are taught, including for IP-routers and digital signal processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.