Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing
US6477635B1 · kind B1 · utility
19Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. A real address tag is utilized to correct for effective address aliasing within the load/store unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.