Structure and method with which to generate data background patterns for testing random-access-memories
US6477673B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Programmability of the data background patterns used to test random-access-memories (RAMs) is accomplished by adding to the memory input/output (I/O) buffers of RAM memory, for each data bit of a data background pattern to be programmed, a programming mechanism and a selection mechanism. The programming mechanism is capable of programming a data bit of the data background pattern in accordance with a programming information signal provided to the RAM. The selection mechanism provides either the programmed data bit or a normal, application data bit to an input/output buffer of the RAM in accordance with whether the RAM is in a test mode or a normal operating mode, as indicated by a test control signal provided to the RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.