Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements

US6477674B1 · kind B1 · utility

Assignee

• Intel Corporation · US

Inventors

• Sarah E. Bates · Temecula, US
• R. Tim Frodsham · Portland, US
• Nasser A. Kurd · Portland, US
• Anne Meixner · Beaverton, US
• David O'Brien · Atlanta, US
• Rajay R. Pai · Beaverton, US
• Mike Tripp · Forest Grove, US
• Jeff Wight · Beaverton, US

Key dates

• Filing date: Dec 29, 1999
• Grant date: Nov 5, 2002
• Expiry date: Dec 29, 2019

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31716
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circuit is operating in a loopback test mode. According to a further embodiment, the integrated circuit includes one or more programmable delay circuits coupled to the I/O buffers that permit switching state (AC) loopback timing tests to be conducted.