Contact escape pattern
US6479319B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Apr 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate for electrically connecting to an integrated circuit, where the integrated circuit has differential pairs of signals that are associated with differential pairs of integrated circuit contacts. Differential pairs of substrate contacts are disposed on a first substrate layer in alignment with the differential pairs of integrated circuit contacts. Differential pairs of vias are also disposed on the first substrate layer, and extend to at least one underlying substrate layer. The differential pairs of vias make electrical connections with the differential pairs of substrate contacts. Each via within a given one of the differential pairs of vias is disposed within a column with each other on the first substrate layer. The columns for each of the differential pairs of vias are in a substantially parallel arrangement one with another. Differential pairs of traces are disposed on the at least one underlying substrate layer. The differential pairs of traces make electrical connection with the differential pairs of vias. Each trace within a given one of the differential pairs of traces is disposed adjacent each other, and routed to a peripheral portion of the at least one underly…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.