Inventor · San Jose, CA, US

Leonard L. Mora

10Patents
5h-index
10Co-inventors
59Inventor score

Filing activity: Jul 23, 1993 → Feb 21, 2008

Most-cited inventions

PatentTitleAreaCited byStatus
US5491362A Package structure having accessible chip Emerging Cross-Sectional Technologies 41 Expired
US5687474A Method of assembling and cooling a package structure with accessible chip Emerging Cross-Sectional Technologies 15 Expired
US6891260B1 Integrated circuit package substrate with high density routing mechanism Electricity 10 Expired
US5539151A Reinforced sealing technique for an integrated-circuit package Electricity 9 Expired
US6777802B1 Integrated circuit package substrate with multiple voltage supplies Electricity 6 Expired
US6479319B1 Contact escape pattern Electricity 5 Expired
US7750460B2 Ball grid array package layout supporting many voltage splits and flexible split locations Electricity 1 Active
US7804167B2 Wire bond integrated circuit package for high speed I/O Electricity 1 Active
US6748576B2 Active trace rerouting Electricity 0 Expired
US6264778A Reinforced sealing technique for an integrated circuit package Electricity 0 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.