One-step semiconductor stack packaging method
US6479321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Mar 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method that applies one time of reflow after stacking a plurality of semiconductor elements to complete the packaging. The upper surface of the chip carrier substrate (opposite side to the chip) in a semiconductor packaging element is implanted with solder balls or coated with solder paste. After stacking a plurality of the semiconductor packaging elements together, a reflow is applied to achieve electrical and physical connections among substrates. If the semiconductor packaging elements are ultra-thin elements, then one only needs to implant solder balls or coat solder paste on the substrate top surface of the top semiconductor packaging element and the substrate bottom surface of the bottom semiconductor packaging element. The reflow will make the soldering material permeate through each layer of substrate, completing the electrical connection between substrates. This type of one-step stack packaging can simultaneously satisfy the requirements of high packaging densities, simple manufacturing processes and low costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.