Method of fabricating a self-aligned non-volatile memory cell
US6479351B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2000 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Nov 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.