Method of fabricating high voltage power MOSFET having low on-resistance
US6479352B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Jan 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Test structures for a high voltage MOSFET are provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. A plurality of trenches are located in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches. The test structures allow the simultaneous optimization of the breakdown voltage and on-resistance of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.