Method for making semiconductor devices having contact plugs and local interconnects
US6479377B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Jun 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.