Patent · US Expired

Method for making a dual damascene interconnect using a multilayer hard mask

US6479391B2 · kind B2 · utility

48Cited by
6References
7Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 22, 2000
Grant dateNov 12, 2002
Priority date—
Expiry dateDec 22, 2020

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76813
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An improved method for making a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A layer of photoresist is deposited and patterned to expose part of the second hard masking layer to define a via. That exposed part of the second hard masking layer is then etched. A second layer of photoresist is deposited and patterned to expose a second part of the second hard masking layer to define a trench. After etching the exposed second part of the second hard masking layer, a via and trench are etched into the dielectric layer, which are then filled with a conductive material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.