Method for complementary oxide transistor fabrication
US6479847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 1999 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | May 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of manufacturing an integrated circuit device includes forming a laminated structure having a first side and a second side, the first side includes a first type Mott channel layer and the second side includes a second type Mott channel layer. A first source region and a first drain region is formed on the first side, a second source region and a second drain region is formed on the second side, a first gate region is formed on the second side, opposite the first source region and the first drain region and a second gate region is formed on the first side, opposite the second source region and the second drain region. The first source, the first drain and the first gate comprise a first type field effect transistor and the second source, the second drain and the second gate comprise a second type field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.