Memory device with divided bit-line architecture
US6479851B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 2000 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | May 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line, shared sense amplifier configuration, two adjacent memory sub-arrays are generally located between two banks of sense amplifiers and selected bit lines of the two adjacent memory sub-arrays are generally connected to metal lines with metal contacts to reduce capacitive loading. Under the present invention, some sense amplifiers from either banks of sense amplifiers are repositioned to the area between the two adjacent memory sub-arrays thereby permitting the repositioned sense amplifiers to be shared. As a result, any two adjacent memory sub-arrays share a bank of sense amplifiers. Furthermore, selected bit lines from the two adjacent memory sub-arrays are coupled to metal lines within the repositioned sense amplifiers. In addition, equilibration circuits are similarly relocated to the area between the two adjacent memory sub-arrays thereby permitting selected bit lines and metal lines to be precharged and equalized in a shorter period of time. By reducing the precharge time, faster memory access can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.