Electrostatic discharge (ESD) latch-up protective circuit for an integrated circuit
US6479871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Apr 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
The ESD protective circuit proceeds from a modified lateral pnpn “latch-up” protective structure having a highly doped n-type zone, which is arranged on the well boundary, along that section of the periphery of the well which runs between the two oppositely doped regions. The highly doped zone is formed of pads arranged with intermediate spacing along the section of the periphery of the well. The result is a low triggering voltage in conjunction with a low on resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.