Settable digital CMOS differential sense amplifier
US6480036B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Nov 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.