High-speed sample-and-hold circuit with gain
US6480128B1 · kind B1 · utility
8Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sample-and-hold system that includes a first source follower having an input and an output and a second source follower that includes an input connected in series with the output of the first source follower and that furthermore comprises of a sample-and-hold switch connected to an output of the second source follower.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.