Semiconductor non-volatile storage
US6480418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Sep 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.