Contactless flash memory with shared buried diffusion bit line architecture
US6480422B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Jun 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A contactless Flash memory uses a bank architecture with bank select devices and/or source line contacts at both ends of each bank. During programming, bank select devices at both ends of the bank supply currents to the memory cell being programmed, and/or diffused source lines conduct currents in both directions away from the memory cell being programmed. The multiple current paths reduce the current in any portion of the diffused lines and thereby reduce voltage drops in the diffused lines during programming. Accordingly, banks can have longer diffused lines (e.g., with twice as many cells per column of a bank) and still employ small bank select devices. The longer bank columns and smaller bank select devices result in an overall decrease in integrated circuit area for bank select devices, even though each bank has two bank select devices per diffused bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.