Providing equal cell programming conditions across a large and high density array of phase-change memory cells
US6480438B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Jun 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide equal cell programming conditions, the integrated circuit device has a number of bitline compensation elements each coupled in series with a separate bitline, and a number of wordline compensation elements each coupled in series with a separate wordline. The resistances in these compensation elements are such that a variation in a sum of (1) the resistance along the corresponding bitline of a cell between the first terminal of the cell and a far terminal of the bitline compensation element that is coupled to the corresponding bitline and (2) the resistance along the corresponding wordline of the cell between a second terminal of the cell and a far terminal of the wordline compensation element that is coupled to the corresponding wordline, is minimized across the cells of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.