Reducing internal bus speed in a bus system without reducing readout rate
US6480921B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1999 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Jul 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved bus system having input ports and output ports for transporting data is described. The bus system includes bus lines, switching elements, and a sequencing element. The bus lines channel data from the input ports to the output ports. The switching elements are configured to place data from the input ports onto the bus lines. Each of the switching elements enable one of a group of data to be placed on each of the bus lines simultaneously. The sequencing element selects a predetermined number of the group of data on the bus lines and sequentially directs the selected number of data to the output ports at different points in time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.