IC substrate noise modeling including extracted capacitance for improved accuracy
US6480986B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2000 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Mar 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for extracting the capacitance value associated with a PN junction along the well-substrate interface for use in modeling the substrate. The method includes receiving the 2-D or 1-D mesh doping profile. The method includes finding a junction curve or transition region that represents the transition between the well and the substrate bulk. The method further includes finding a set of parameters &agr;,&bgr; and &ggr; to characterize the junction at a point or a vertical discretization along the transition. During modeling, the set of parameters &agr;, &bgr; and &ggr; is then employed, along with the input bias voltage value, to calculate the thickness of the depletion region, which is in turn employed to calculate the capacitance for the well-substrate junction. The capacitance calculated is then employed to more accurately model the junction, which leads to a more accurate model for the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.