Method, apparatus, and program product for laying out capacitors in an integrated circuit
US6480992B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method includes defining at least one sizing parameter for a capacitor arrangement (11). Once the parameter or parameters are defined, the method includes applying at least one sizing parameter to select a particular capacitor arrangement (11) for a free area on the integrated circuit chip (12). The selected capacitor arrangement comprises the largest arrangement which is accommodated within the free area, subject to the sizing parameter or parameters employed. Sizing parameters may include a height dimension range between a maximum and minimum height dimension for the capacitor arrangement, and permissible width dimensions for the capacitor arrangement. Steps in the layout method may be performed on a computer system (51) under the control of operational program code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.