Semiconductor device fabricating method
US6482662B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2000 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Apr 10, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/945
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of fabricating a semiconductor device is provided that includes forming first and second gate electrodes on a substrate via a first photo mask, in which the first and second gate electrodes are in a longitudinal direction parallel to respective channels arranged in x-axis y-axis directions, measuring and comparing the lengths of the first and second gate electrodes on the substrate, estimating a mask bias on the basis of the difference between the actually measured lengths of the gate electrodes, and forming patterns of the first and second gate electrodes of which lengths are adjusted with the estimated mask bias on a new second photo mask, so that the first and second gate electrodes of the same length are formed on the same substrate via the new, second photo mask, regardless of the arrangement directions of the gate electrodes in parallel to channels. This has the effect of improving the processing speed of high CPU or logic element and the yield of products manufactured by this process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.