Circuit board having burr free castellated plated through holes
US6483046B1 · kind B1 · utility
1Cited by
20References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2000 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Apr 24, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a circuit board having burr free castellated plated through holes. In particular, the leading edge of the plated through hole, that tends to produce burr formation during conventional profiling, is removed or pre-profiled to off-set the leading edge of the plated through hole from a surface of the circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.