Semiconductor device package structure
US6483178B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 2000 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Jul 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device package structure is proposed, which allows the encapsulation body to be highly secured in position to the leads, making the encapsulation body hardly delaminated from the leads. The proposed semiconductor device package structure comprises a die pad; a semiconductor chip mounted on the die pad; a plurality of leads arranged around the die pad, each lead being formed with a bolting hole; a plurality of bonding wires for electrically coupling the semiconductor chip to the leads; and an encapsulation body which encapsulates the semiconductor chip and the bonding wires and includes a part filled in the bolting hole in each of the leads. The bolting hole is characterized in the forming of a constricted middle part or an inclined orientation with respect to the lead surface, which allows the encapsulation body to be highly secured in position to the leads, thereby making the encapsulation body hardly delaminated from the leads. As a result, the finished package product can be highly assured in quality and reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.